DESIGN OF MODIFIED DUAL-CLCG ALGORITHM FOR PSEUDO-RANDOM BIT GENERATOR

Abstract

Pseudorandom bit generator (PRBG) is an essential component for securing data during
transmission and storage in various cryptography applications. Among popular existing PRBG methods
such as linear feedback shift register (LFSR), linear congruential generator (LCG), coupled LCG (CLCG),
and dual-coupled LCG (dual-CLCG), the latter proves to be more secure. This method relies on the
inequality comparisons that lead to generating pseudorandom bit at uniform time interval. Hence, a new
architecture of the existing dual- CLCG method is developed that generates pseudo-random bit at uniform
clock rate. A new PRBG method called as “modified dual-CLCG” and it’s very large-scale integration
(VLSI) architecture are proposed in this paper to mitigate the aforesaid problems. The novel contribution
of the proposed PRBG method is to generate pseudorandom bit at uniform clock rate with one initial
clock delay and minimum hardware complexity.